1. Technical Field
The present invention relates to high dielectric insulating layers for use in transistors, and in particular, organic layers.
2. Description of the Related Art
A typical field effect transistor (xe2x80x9cFETxe2x80x9d) starts with a gate electrode applied to a substrate. An insulating layer then is applied on top of the gate electrode, sometimes overlapping onto the substrate. Source and drain electrodes then are applied on top of the insulating layer, spaced slightly apart with the gap between them positioned above the gate electrode. Finally, a layer of semiconductor is applied to fill the gap between the source and drain electrodes, often overlapping onto the top of the source and drain electrodes. The presence or absence of an appropriate voltage at the gate electrode then will drive the semiconductor into its conductive or non-conductive states, either electrically connecting or disconnecting the source and drain electrodes.
In an FET made with a semiconductor, some carriers (holes or electrons, depending on whether the semiconductor is a p-type or n-type semiconductor) in the semiconductor will be induced at the interface between the gate insulator and the semiconductor when a voltage is applied to the gate electrode. The carriers induced by this low gate bias voltage will first fill the trap levels, but may not be enough to completely fill those levels. Therefore, even at high drain voltages but at low gate bias voltages, one still cannot collect pronounced free carriers that can move freely from the source side to the drain side.
When the gate bias voltage is high enough (greater than a threshold voltage, VT), more carriers will be induced. They can not only fill all the trap levels, but also have excessive carriers left, which can then be pushed to the conduction band of the semiconductor, where they are free to move. The potential difference between the drain and the source electrodes will then drive those free carriers to move from the source electrode to the drain electrode.
The current-voltage characteristics for a FET device are qualitatively modeled by the following equations:
Linear Region: |VGSxe2x88x92VT51  greater than |VDS|xe2x80x83xe2x80x83(1)
      I    D    =                    Wc        i            L        ⁢          μ      ⁡              (                              V            GS                    -                      V            T                    -                                    V              DS                        /            2                          )              ⁢          V      DS      xe2x80x83Saturation Region: |VGSxe2x88x92VT|xe2x89xa6|VDS|xe2x80x83xe2x80x83(2)
      I    D    =                    Wc        i                    2        ⁢        L              ⁢                  μ        ⁡                  (                                    V              GS                        -                          V              T                                )                    2      
in which:
ci is the capacitance per unit area of the gate electrode=C/A;
xcexc is the field-effect mobility of the semiconductor;
ID is the current through the drain electrode;
L is the channel length between the source electrode and the drain electrode;
VDS is the voltage between the drain and source electrodes;
VGS is the voltage between the gate and source electrodes;
VT is the threshold voltage described above; and
W is the width of the channel, i.e., the width of the source and drain electrode pads.
The geometric parameters of the FET, such as the channel length and width, are defined by the mask pattern used to make the FET, and will certainly affect the device performance. As will be apparent from the equations, it is desirable to keep them as small as possible to achieve high current and high resolution (or high density). However, the size of the patterns usually is dictated mostly by the manufacturing process used to generate the patterns, with more sophisticated (and expensive) equipment needed to generate very small pattern sizes.
The equations highlight two other parameters which can potentially be adjusted as needed to achieve high currents at low operating voltages (VDS and VGS), namely, generating a high capacitance and high field effect mobility to get a high current, ID. High mobility usually is a function of the semiconductor used. High capacitance is dependent on the thickness of the insulating layer (the thinner, the better) and the dielectric constant of the insulating layer (the higher, the better). Therefore, one way to maximize the current ID at low voltages is to provide a thin insulating layer formed of a material with a high dielectric. At the same time, the insulating layer should be free of pinholes and have a high breakdown voltage to continue functioning as an insulator even when it is very thin. It also needs to be compatible with the subsequent processes needed to complete device and circuit fabrications, which means it should have a good chemical resistance.
Conventionally, all of the layers involved are inorganic materials. Most commonly, the substrate is crystalline silicon, the electrodes are metal, the insulating layer is silicon dioxide and the semiconductor is crystalline, polycrystalline or amorphous silicon. Well known alternatives use III-V semiconductors, such as gallium arsenide. All are characterized by high processing temperatures well in excess of 200xc2x0 C.
Recently, there has been considerable interest in developing an organic field effect transistor (xe2x80x9cOFETxe2x80x9d). OFETs have the following potential advantages when compared with inorganic FETs:
(1) They can be produced using low cost processing methods, e.g., spin coating, web coating, inkjet printing and vacuum evaporation to form the active layers. It is even possible to do this on a moving web, rather than in batches on crystalline or glass wafers.
(2) They provide excellent compatibility with many different kinds of substrates (e.g., flexible plastic substrates, glass, metal foils, etc.), and can be made in very large sizes, i.e., they are not limited to the size to which crystals can be grown.
(3) The molecular structures and orientation for both the organic semiconductors and the substrates can be tailored with desired properties.
Due to these potential benefits, dramatic progress has been made in the development of OFETs, attracting increasing attention in both academic and industrial laboratories around the world. Gundlach, D. J., Kuo, C-C., Nelson, S. F., and Jackson, T. N., xe2x80x9cOrganic thin film transistors with field effect mobility  greater than 2 cm2/V-s,xe2x80x9d 57th Annual Device Research Conference Digest, pp. 164-165, June, 1999, reported pentacene-based OFETs with a field effect mobility as large as 2.1 cm2/V-s, which is higher than amorphous silicon. Dimitrakopoulos, C. D., Purushothaman, S., Kymissis, J., Callegari, A., Shaw, J. M., xe2x80x9cLow-voltage organic transistors on plastic comprising high-dielectric constant gate insulators,xe2x80x9d Science, Feb. 5, 1999, Vol. 283, pp. 822-824, reported OFETs with a low operating voltage ( less than 5 V) and a high mobility (xcx9c0.4 cm2/V-s) by employing a high dielectric constant insulating film using barium zirconate titanate (BZT) and barium strontium titanate (BST) on a polycarbonate substrate.
OFETs are considered strong candidates for use in integrated circuits (ICs) in applications such as radio frequency identification (RFID) tags, digital displays, digital logic circuits and many other applications.
Unfortunately, one of the disadvantages to using OFETs is that the materials involved cannot withstand the high processing temperatures used with conventional inorganic materials. For example, the 200+xc2x0 C. temperatures needed to process conventional inorganic materials would at the very least cause a polymeric substrate to deform, and might cause further breakdown of the polymer or even ignition at high enough temperatures. Deformation is highly undesirable, since each layer of the structure has to be carefully registered with the layers below it, which becomes difficult to impossible when the layers below it are deformed due to processing temperatures.
SiO2, SiNx, AlOx, and TaOx are the most popular dielectric materials employed in both inorganic and organic semiconductor FETs. However, the conventional methods for depositing these materials, such as chemical vapor deposition (CVD) and plasma enhanced CVD, need high temperatures ( greater than 300xc2x0 C.) which are not compatible with polymeric substrates. Without such high processing temperatures, poor film quality and pinholes are typically unavoidable, resulting in poor insulating properties. Another widely used process is ion beam deposition, but it needs high vacuum and expensive equipment which are incompatible with the goal of very low cost production. Similarly, use of BZT and BST need either a high firing temperature (400xc2x0 C.) for the sol-gel process, or radio-frequency magnetron sputtering, which also requires vacuum equipment, and may also have stoichiometric problems.
In addition, the dielectric constants for these materials other than TaOx are not high enough to achieve the low operating voltage and high current which are desirable features for display drivers and other likely applications for OFETs. Likewise, the organic films which have been considered, such as polyimide, polyester, and epoxy, do not have the desired high dielectric constants, and thus need undesirable high voltages to operate OFETs. Bao, Z., Rogers, J. A., and Katz, H. E., xe2x80x9cPrintable organic polymeric semiconducting materials and devicesxe2x80x9d, J. Mater. Chem., 1999, Vol. 9, pp. 1895-1904; Bao, Z., and Lovinger, A. J., xe2x80x9cSoluble regioregular polythiophene derivatives as semiconducting materials for field-effect transistorsxe2x80x9d, Chem. Mater., 1999, Vol. 11, pp. 2607-2612; Bao, Z., xe2x80x9cMaterials and fabrication needs for low cost organic transistor circuitsxe2x80x9d, Adv. Mater., 2000, Vol. 12, No. 3, pp. 227-230.
The insulating layers in some discrete and integrated circuit capacitors are formed using a polymeric matrix loaded with ceramic particles to increase the dielectric constant of the polymer alone. The ceramic particles used in such materials typically range in average diameter from 500 to 3000 nm, the insulating layer is over 10,000 nm thick and the polymer matrix typically is loaded with at least 50% ceramic particles, and usually much more. See, e.g., U.S. Pat. No. 3,660,328 (Lindquist) and WO 92/18218 (Du Pont).
Such systems would not work in the insulating layer of a typical transistor because the ceramic grains are simply too large to fit. In contrast to the 10,000+ nm thickness of the insulating layer in a capacitor, the insulating layer in a transistor normally is no more than 500 nm. This means that the grain sizes can be no more than about 200 nm to be able to coat the layer.
Unfortunately, there is a reason particles between 500 and 3000 nm are used in capacitorsxe2x80x94that particle size is the range in which the dielectric constant of the particles peaks. As shown in FIG. 2 of Shaikh, A. S., Vest, R. W., and Vest, G. M., xe2x80x9cDielectric properties of ultrafine grained BaTiO3xe2x80x9d, EEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, July 1989, Vol. 16, No. 4, pp. 407-412, the dielectric constant of ceramic particles plummets as the grain size moves below about 500 nm, so simply substituting smaller grains would not normally be expected to work.
According to the present invention, a material is provided for use as an insulating layer, which is formed of superfine ceramic particles dispersed in a polymeric matrix. The characteristics of the material can be varied by varying the selection and relative concentrations of the ceramic particles and matrix components. Appropriate selection can provide high dielectric constant materials that are not subject to pinholes, have a high voltage breakdown and are chemically resistant.
The ceramic particles should be less than xcx9c200 nm, preferably less than xcx9c100 nm, and probably about xcx9c50 nm in average diameter. The particles can be formed from a variety of materials. Each particle can be formed from a single one or a combination of these materials. The particles included in the layer can all be uniform, or can vary in material composition and/or size.
The polymeric matrix can be a polymer, such as an epoxy resin, formed from a variety of monomeric materials.
The characteristics of the insulating layer can be adjusted by appropriate selection and combination of materials. The minimum coating thickness can be varied by adjusting the particle size and percent solids in the polymeric matrix, while the dielectric constant can be varied by adjusting the ratio and selection of ceramic particles to the matrix material.
The insulating layer of the present invention can be applied using a wide variety of techniques, such as spin-coating, slide or bar coating, gravure printing, and inkjet printing. Some of these application techniques will allow patterning of the coating, so that circuits can be laid down easily and continuously. Generally speaking, these materials are not sensitive to air exposure during the manufacturing process, so the entire process can be carried out in a normal environment, without the need for expensive vacuum equipment.
As will be apparent, the combination of the inorganic ceramic particles into the organic matrix combines the best of both types of materials, namely, the high dielectric properties of the ceramic particles are combined with the flexible application capabilities of the organic matrix. In addition, due to the wide range of potential combinations of materials, the characteristics of the layer can be varied easily by adjusting the materials in the mix.